Japanese Patent Application Laid-Open Publication No. 11-204720 (Patent Document 1) discloses a technology in which an electrical connection between stacked semiconductor chips is made by wire bonding in a three-dimensional stacking type SiP (System in Package).
Japanese Patent Application Laid-Open Publication No. 2000-260934 (Patent Document 2) discloses a technology in which electrodes obtained by embedding solder or low melting metal by electrolytic plating method or electroless plating method into through holes formed in semiconductor chips are formed in stacked upper and lower semiconductor chips. Then, after applying heat, the electrodes buried in the through holes of the stacked upper and lower semiconductor chips are connected by the fusion joining, thereby electrically connecting the stacked upper and lower semiconductor chips.
Japanese Patent Application Laid-Open Publication No. 2005-340389 (Patent Document 3) discloses a technology in which a stud bump electrode is formed in an upper semiconductor chip of the stacked semiconductor chips and a through silicon via is formed in a lower semiconductor chip. Then, the stud bump electrode formed in the upper semiconductor chip is deformed and inserted by pressure welding to the through silicon via formed in the lower semiconductor chip to caulk the stud bump electrode and the through silicon via geometrically, thereby electrically connecting the upper and lower semiconductor chips.
Japanese Patent Application Laid-Open Publication No. 2005-93486 (Patent Document 4) discloses a technology of forming an electrode to extend a pad electrode formed on a surface of a silicon substrate via an interlayer insulating film to a rear surface of the silicon substrate. In this technology, a silicon substrate is etched from a rear surface of the silicon substrate with using a hard mask as a mask, thereby forming an opening whose bottom surface is the interlayer insulating film (FIG. 4C of Patent Document 4). Then, after removing the hard mask (FIG. 5A of Patent Document 4), an insulating film is formed on the entire rear surface of the silicon substrate including the inside of the opening (FIG. 5B of Patent Document 4). Thereafter, by etching the interlayer insulating film with using a resist film that covers the sidewall of the opening and the portion other than the opening (FIG. 5C of Patent Document 4) as a mask, the pad electrode is exposed on the bottom surface of the opening (FIG. 6A of Patent Document 4). By this means, a through hole reaching the pad electrode from the rear surface of the silicon substrate can be formed. Further, by embedding a metal material in the through hole, an electrode which is electrically connected to the pad electrode and reaches the rear surface of the silicon substrate can be formed. Note that it is mentioned here that, when removing the hard mask used in etching the silicon substrate, the interlayer insulating film exposed from the bottom surface of the opening is also partly etched and removed.
Japanese Patent Application Laid-Open Publication No. 2006-32699 (Patent Document 5) discloses the manufacturing technology of a semiconductor device as shown below. More specifically, a first insulating film is formed on a front surface of a semiconductor substrate, and a part of the first insulating film is selectively etched from a front surface side of the semiconductor substrate to the middle of the film thickness, thereby reducing the film thickness. By this etching, a concave portion having a bottom surface formed by partly removing the first insulating film is formed. Thereafter, a pad electrode is formed on the first insulating film including the inside of the concave portion (FIG. 16 of Patent Document 5). Subsequently, after forming a second insulating film on a rear surface of the semiconductor substrate, etching is performed so that an opening larger than the concave portion is formed in the second insulting film and the semiconductor substrate at a position corresponding to the concave portion of the first insulating film. By this etching, a via hole which has a hole diameter larger than that of the concave portion and penetrates through the second insulating film and the semiconductor substrate is formed (FIG. 17 of Patent Document 5). Next, after forming a third insulating film on the second insulating film including the inside of the via hole (FIG. 18 of Patent Document 5), the etching is performed from the rear surface of the semiconductor substrate. By this etching, the third insulating film formed on the second insulating film, the third insulating film formed on the bottom surface of the via hole and the first insulating film whose thickness is reduced are removed. By this means, the pad electrode is exposed on the bottom surface of the via hole (FIG. 19 of Patent Document 5). Then, by embedding a metal material in the through hole, an electrode that is electrically connected to the pad electrode and reaches the rear surface of the silicon substrate can be formed.
Japanese Patent Application Laid-Open Publication No. 2007-53149 (Patent Document 6) discloses a technology in which a contact electrode (through silicon via) to be connected to a pad is processed from a rear surface of a semiconductor substrate when stacking a plurality of semiconductor chips. More specifically, after a through hole having a conical opening is formed from a rear surface of the semiconductor substrate, an insulating film is formed on the rear surface of the semiconductor substrate including the inside of the through hole. Then, after removing the insulating film on the bottom surface of the through hole, a conductive film is formed on a wall surface of the through hole and then patterned, thereby forming a contact electrode.
Japanese Patent Application Laid-Open Publication No. 2006-222138 (Patent Document 7) discloses the manufacturing technology of a semiconductor device as shown below. More specifically, a method of forming a through silicon via which penetrates in a thickness direction of a semiconductor substrate is described therein. In this technology, a first insulating film is formed on a front surface of a semiconductor substrate, and a second insulating film is formed on a rear surface of the semiconductor substrate (FIG. 1(a) of Patent Document 7). Then, a first etching stop layer made of a conductive material having an etching rate different from that of the semiconductor substrate is formed on the second insulating film (FIG. 1(b) of Patent Document 7). Next, at a formation position of the through silicon via, a concave portion which penetrates through the first insulating film, the semiconductor substrate and the second insulating film and reaches the first etching stop layer is formed (FIG. 1(c) of Patent Document 7). Thereafter, the through silicon via is formed by embedding a conductive material in the concave portion by the plating method using the first etching stop layer as a seed layer (FIG. 1(d) to FIG. 1(f) of Patent Document 7).